SM8720AV nippon precision circuits inc.? 3-pll multi-output clock generator overview the SM8720AV is a clock generator ic with 3 built-in plls. it can simultaneously output a 27mhz master clock and three other clocks with different frequency (clk1out, clk2out, clk3out) derived from the master clock. the 3 generated clocks can be independently turned on/off using control pins and the fre- quency of clk3out can be switched, allowing unneeded clocks within a system to be switched off thereby reducing current consumption. the master clock, supplied by high-stability crystal oscillator external input, allows clocks to be generated with high precision and low jitter and which require no frequency adjustment, making the SM8720AV ideal for digital still cameras and other applications which require multiple high-preci- sion clocks. features 2.7 to 3.3v supply voltage 21ma typ. current consumption (v dd = 3.0v, all outputs with no load) 27mhz master clock (external input) (internal pll reference clock) generated clocks 27mhz master clock (refout) 22.5792mhz (clk1out) (on/off switching using control pin) 48.0000mhz (clk2out) (on/off switching using control pin) 36/45/48.6mhz (clk3out) (on/off switching using control pin, fre- quency switching) output load 25pf (refout) 15pf (all outputs excluding refout) low jitter output 140ps typ. peak-to-peak (refout) 220ps typ. peak-to-peak (clk1out, clk3out) 220ps typ. peak-to-peak (clk2out) 16-pin vsop package (pb free) applications digital still cameras ordering information pinout (top view) package dimensions (unit: mm) weight: 0.07g device package SM8720AV 16-pin vsop vdd1 1 fin 2 vss1 3 clk3out 4 16 15 14 13 refout vss3 sel2 clk2_on clk3_on 5 sel1 6 clk1_on 7 vdd2 8 12 vdd3 11 clk2out 10 vss2 9 clk1out 4.4 0.2 6.4 0.2 5.1 0.2 1.15 0.1 0.10 0.05 0.5 0.2 0.275typ 0.65 0.10 0.12 m 0.15 + 0.1 - 0.05 0.22 + 0.1 - 0.05 0 to 10
SM8720AV nippon precision circuits inc.? block diagram pin description number name i/o description 1 vdd1 supply voltage 1 2 fin i master clock input (27mhz constant input) 3 vss1 supply ground 1 4 clk3out o clock output 3 (36/45/48.6mhz switchable output) 5 clk3_on i output clock enable 3 (high = enable, low = disable) 6 sel1 i output select 1 7 clk1_on i output clock enable 1 (high = enable, low = disable) 8 vdd2 supply voltage 2 9 clk1out o clock output 1 (22.5792mhz constant output) 10 vss2 supply ground 2 11 clk2out o clock output 1 (48mhz constant output) 12 vdd3 supply voltage 3 13 clk2_on i output clock enable 3 (high = enable, low = disable) 14 sel2 i output select 2 15 vss3 supply ground 3 16 refout o master clock output (27mhz constant output) clk1_on fin reference divider 1 phase detector 1 charge pump 1 lpf 1 vco 1 control logic clk1out loop divider 1 (pll1) reference divider 2 phase detector 2 charge pump 2 lpf 2 vco 2 loop divider 2 (pll2) reference divider 3 phase detector 3 charge pump 3 lpf 3 vco 3 loop divider 3 (pll3) clk2_on clk3_on clk2out clk3out sel2 sel1 refout
SM8720AV nippon precision circuits inc.? absolute maximum ratings v dd = (v dd1 , v dd2 , v dd3 ), v ss = (v ss1 , v ss2 , v ss3 ) unless otherwise noted. recommended operating conditions v ss = (v ss1 , v ss2 , v ss3 ) = 0v, unless otherwise noted. electrical characteristics dc characteristics f fin = 27.0000mhz, v dd = (v dd1 , v dd2 , v dd3 ) = 3.0 0.3v, v ss = (v ss1 , v ss2 , v ss3 ) = 0v, ta = ? 40 to +85 c unless otherwise noted. parameter symbol rating unit supply voltage range v dd1 , v dd2 , v dd3 ? 0.3 to 6.5 v supply voltage deviation v dd1 ? v dd2 , v dd1 ? v dd3 , v dd2 ? v dd3 ?.1 v input voltage range v in ? 0.3 to v dd + 0.3 v output voltage range v out ? 0.3 to v dd + 0.3 v power dissipation p d 165 mw storage temperature range t stg ? 55 to 125 c parameter symbol conditions rating unit min typ max supply voltage *1 *1. the supply voltages are with reference to v ss = 0v. it is recommended that the voltages applied to pins vdd1, vdd2, vdd3 be supplied from a single source. if various voltage sources are used on pins vdd1, vdd2, vdd3, the voltage supplies should be applied simultaneously. if the tim ing of applying voltage supplies varies, the device may be damaged. v dd1 , v dd2 , v dd3 2.7 3.3 v output load capacitance 1 c l1 refout output 25 pf output load capacitance 2 c l2 clk1out, clk2out, clk3out outputs 15 pf master clock frequency f fin external clock input 27.0000 mhz operating temperature t opr ? 40 +85 c parameter symbol pins conditions rating unit min typ max current consumption i dd vdd v dd = 3.0v, ta = 25 c, all outputs operating without load ?128ma input voltage v ih fin, sel1, sel2, clk1_on, clk2_on, clk3_on *1,*2 *1. clk1_on, clk2_on, clk3_on pins have schmitt-trigger inputs with internal pull-down resistance. v dd = 3.0v 0.8v dd v v il 0.2v dd v input current i ih1 clk1_on, clk2_on, clk3_on *1 v in = v dd ?080 a i il1 v in = 0v ? 1 a i ih2 fin, sel1, sel2 *2 *2. sel1, sel2 pins have schmitt-trigger inputs. v in = v dd 1 a i il2 v in = 0v ? 1 a output voltage v oh all outputs i oh = ? 2ma v dd ? 0.4 v v ol i ol = 2ma 0.4 v
SM8720AV nippon precision circuits inc.? ac characteristics f fin = 27.0000mhz, v dd = (v dd1 , v dd2 , v dd3 ) = 3.0 0.3v, v ss = (v ss1 , v ss2 , v ss3 ) = 0v, ta = ? 40 to +85 c unless otherwise noted. parameter symbol pins conditions rating unit min typ max external input clock frequency f fin fin external clock input 27.0000 mhz external clock duty cycle *1 *1. when using an external clock input, it is recommended that fin duty cycle = 50%, clock signal amplitude = v dd level. note that the input signal voltage amplitude should not exceed the absolute maximum rating, otherwise the device may be damaged. dt fin fin ta = 25 c, v i = 0.5v dd , external clock input 45 50 55 % output clock rise time *2 *2. measured using the circuit shown in ?ure 1 on the npc standard evaluation board. t r refout c l = 25pf, v ol = 0.2v dd to v oh = 0.8v dd transition 3.0 ns all outputs excluding refout c l = 15pf, v ol = 0.2v dd to v oh = 0.8v dd transition 4.0 ns output clock fall time *2 t f refout c l = 25pf, v oh = 0.8v dd to v ol = 0.2v dd transition 3.0 ns all outputs excluding refout c l = 15pf, v oh = 0.8v dd to v ol = 0.2v dd transition 4.0 ns output clock jitter (peak-to-peak) *3,*4 *3. measured using the circuit shown in ?ure 2 on the npc standard evaluation board. *4. measured using master clock input on fin with 80ps (peak-to-peak) jitter. t jitter refout ta = 25 c, c l = 25pf, v o = 0.5v dd 140 200 ps clk1out, clk3out ta = 25 c, c l = 15pf, v o = 0.5v dd 220 350 ps clk2out ta = 25 c, c l = 15pf, v o = 0.5v dd 220 500 ps output clock duty cycle dt refout *2,*5 *5. measured using master clock input on fin with duty cycle = 50%, clock signal amplitude = v dd level. ta = 25 c, c l = 25pf, v o = 0.5v dd 45 50 55 % all outputs excluding refout *2 ta = 25 c, c l = 15pf, v o = 0.5v dd 45 50 55 % power-up time *2,*6 *6. the power-up time is the time from supply off/on transition or enable low/high transition until each output clock reaches it s designated frequency to within ?.1%. t p all outputs excluding refout ?5ms figure 1. measurement circuit 1 figure 2. measurement circuit 2 frequency & time interval analyzer (hp5371a) 27mhz oscilloscope (infinium hp54845a) passive probe (hp10435a) active probe (hp1152a) dut dut:device under test jitter measurement system (asa, m1) oscilloscope (hp54720d +hp54721a) active probe (hp54701a) dut dut:device under test 27mhz
SM8720AV nippon precision circuits inc.? functional description 27mhz master clock the 27mhz master clock is an external clock input on pin fin as shown in gure 3. it is recommended that the master clock have 27.0000mhz frequency, 50% duty, and v dd level amplitude. note that the fin input clock amplitude voltage level should not exceed the absolute maximum rating, other- wise the device may be damaged. output clock frequency the SM8720AV generates 3 output clocks with frequency 22.5792mhz (clk1out), 48mhz (clk2out), and 36/45/48.6mhz (clk3out), derived from the master clock. in addition, the 27mhz master clock is out- put on refout. a list of the supported clock frequency and control settings is shown in table 1. figure 3. external clock input table 1. output clock frequency (27.0000mhz master clock frequency) clk1_on (pin 7) clk2_on (pin 13) clk3_on (pin 5) output clock frequency [mhz] refout (pin 16) clk1out (pin 9) clk2out (pin 11) clk3out (pin 4) sel1 = h (pin 6) sel2 = l (pin 14) sel1 = l (pin 6) sel2 = l (pin 14) sel1 = l (pin 6) sel2 = h (pin 14) h h h 27.0000 22.5792 48.0000 36.0000 45.0000 48.6000 l 27.0000 l 48.0000 36.0000 45.0000 48.6000 h l 27.0000 22.5792 l 36.0000 45.0000 48.6000 l 27.0000 l l 36.0000 45.0000 48.6000 h h l 27.0000 22.5792 48.0000 l l l l 27.0000 l 48.0000 l l l h l 27.0000 22.5792 llll l 27.0000 lllll internal circuits fin (pin 2) refout (pin 16) external clock
SM8720AV nippon precision circuits inc.? nc0119ae 2002.07 please pay your attention to the following points at time of using the products shown in this document. the products shown in this document (hereinafter ?roducts? are not intended to be used for the apparatus that exerts harmful in?ence on human lives due to the defects, failure or malfunction of the products. customer are requested to obtain prior written agreemen t for such use from nippon precision circuits inc. (hereinafter ?pc?. customers shall be solely responsible for, and indemnify and hold npc free and harmless from, any and all claims, damages, losses, expenses or lawsuits, due to such use without such agreement. npc reser ves the right to change the speci?ations of the products in order to improve the characteristic or reliability thereof. npc makes no c laim or warranty that the contents described in this document dose not infringe any intellectual property right or other similar right owned by third parties. therefore, npc shall not be responsible for such problems, even if the use is in accordance with the descriptions provided in t his document. any descriptions including applications, circuits, and the parameters of the products in this documents are for reference to us e the products, and shall not be guaranteed free from defect, inapplicability to the design for the mass-production products without further te sting or modi?ation. customers are requested not to export or re-export, directly or indirectly, the products to any country or any ent ity not in compliance with or in violation of the national export administration laws, treaties, orders and regulations. customers are req uested appropriately take steps to obtain required permissions or approvals from appropriate government agencies. nippon precision circuits inc. 4-3, fukuzumi 2-chome, koto-ku, tokyo 135-8430, japan telephone: +81-3-3642-6661 facsimile: +81-3-3642-6698 http://www.npc.co.jp/ email: sales @ npc.co.jp
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